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Tareq Ahmad Alawneh was born in Irbid, Jordan, in 1984. He received the B.S. and M.S. degrees in computer engineering from the Jordan University of Science and Technology (JUST), Irbid, in 2006 and 2009, respectively, and the Ph.D. degree in computer engineering from the University of Hertfordshire, U.K., in 2021. From 2010 to 2013, he was a full-time Lecturer with the Electrical and Computer Engineering Department, Tafila Technical University (TTU), Al-Tafila, Jordan. He was an Assistant Professor with Fahad Bin Sultan University (FBSU), Saudi Arabia, in 2021. He is currently an Assistant Professor with the Electrical Department, Al-Balqa Applied University. His research interests include cache partitioning algorithms, low-power and high-performance designs, Dynamic random access memory (DRAM) and cache memories, multi-core systems, IoT, deep and machine learning, Chip multiprocessors (CMPs) systems, image processing, algorithms, network security, computer networks, and embedded systems.
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 Research Intersets:
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Computer architecture
IoT
Network security
Deep and machine learning
Computer networks
Low-power, high-reliable, and high-performance designs
Image processing
Medical image analysis
DRAM and cache memories
Multi-core processors
Tiled-chip multiprocessors
Chip-multiprocessors architectures
Embedded systems
Algorithms
Digital integrated circuits
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 Qualifications
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Degree
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University
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Specialization
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Graduation year
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| 1 | PHD | University of Hertfordshire | Computer Engineering | 2021 | | 2 | MASTER DEGREE | Jordan University of Science and Technology | Computer engineering | 2009 | | 3 | BACHELOR'S DEGREE | Jordan University of Science and Technology | Computer Engineering | 2006 |
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 Experiences
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Academic Experience:
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 2021 -2022 :Assistant professor,Fahad Bin Sultan University,Saudi Arabia.
2010 -2013 :Full-time lecturer,Tafila Technical University,Jordan.
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Administrative Experience:
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 Publications
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1- A Hardware-Based Approach to Determine the Frequently Accessed DRAM Pages for Multi-Core Systems ,IEEE ACCESS, 2023,Vol. 1,no. 1.
2- High-Performance and Power-Saving Mechanism for Page Activations Based on Full Independent DRAM Sub-Arrays in Multi-Core Systems ,IEEE ACCESS, 2023,Vol. 11,no. .
3- Hybrid Chain: Blockchain Enabled Framework for Bi-Level Intrusion Detection and Graph-Based Mitigation for Security Provisioning in Edge Assisted IoT Environment ,IEEE ACCESS, 2023,Vol. 11,no. .
4- Dynamic Fine-Grained Activation Mechanism for Multi-core
Systems ,In proceedings of the 18th ACM International Conference on Computing Frontiers, 2021,Vol. ,no. .
5- A Dynamic Row-Buffer Management Policy for Multimedia Applications ,In proceedings of the 27th IEEE Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP, Pavia, Italy, 2019,Vol. ,no. .
6- A prefetch-aware memory system for data access patterns in multimedia applications ,In proceedings of the 15th ACM International Conference on Computing Frontiers, Ischia, Italy, 2018,Vol. ,no. .
7- A Data Access Prediction Unit for Multimedia Applications ,In proceedings of 28th IEEE International Conference on Microelectronics, ICM, 2016,Vol. ,no. .
8- A Proximity Scheme for Instruction Caches in Tiled CMP
Architectures ,In proceedings of the 26. GI/ITG Workshop Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware, PARS, Potsdam, Germany, 2015,Vol. ,no. .
9- Proximity Coherence for Instruction Caches in Tiled CMP Architectures ,In proceedings of the 10th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2014), High Performance and Embedded Architecture and Compilation, HiPEAC, Fiuggi, Italy, 2014,Vol. ,no. .
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 University Courses Taught
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1- Advanced computer architecture + Computer architecture and organization Lab.
2- Parallel processing systems + Parallel processing systems lab.
3- Object-oriented programming + Object-oriented programming Lab.
4- Design and analysis of algorithms.
5- Data structures.
6- Special topics in computer engineering.
7- Computer network Lab + Computer network security Lab.
8- Digital Logic Design Lab.
9- Data structure and algorithms + Data structure and algorithms Lab.
10- Microprocessor Systems + Microprocessor Systems lab.
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 Master and Phd thesis contributions
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Thesis Defense Committee Membership
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Support Security Decision in Identifying SIP Attach Based on Machine Learning ,Fahad Bin Sultan University,Master Thesis,2022.
Honepot Coupled Adaptive Neuro Fuzzy Inference Model for DDoS Attack Detection ,Fahad Bin Sultan University,Master Thesis,2022.
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 Conferences and Workshops
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Conference/Workshop Name
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Conference/Workshop Place
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Conference/Workshop Date
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| 1 | The 2023 IEEE Jordan 2023 International Joint Conference on Electrical Engineering and Information Technology (JEEIT 2023) | Jordan | 2023/05 | | 2 | The 18th ACM International 2021 Conference on Computing Frontiers (CF 2021) | Italy | 2021/05 | | 3 | The 27th IEEE Euromicro International 2019 Conference on Parallel, Distributed and Network-Based Processing (PDP 2019) | Italy | 2019/03 | | 4 | The 15th ACM International 2018 Conference on Computing Frontie (CF 2018) | Italy | 2018/05 | | 5 | The 28th IEEE International Conference on Microelectronics (ICM) | Egypt | 2016/12 | | 6 | The 10th International 2014 Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2014) | Italy | 2014/07 | | 7 | The 26. GI/ITG Workshop Parallel 2015 -Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2014) | Germany | 2014/05 |
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 Journals Editor/ Reviewer
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Review:
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IEEE ACCESS.
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 Other Contributions:
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*External reviewer in the 17th International Workshop on Software and Compilers for Embedded Systems (SCOPES), Sankt Goar, Germany.
*External reviewer in the 32nd IEEE International Conference on Computer Design (ICCD), Seoul, South Korea.
*External reviewer in the 18th Euromicro Conference on Digital System Design (DSD), Madeira, Portugal.
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